Successive approximation register (SAR) analog-to-digital converters (ADC) determine each bit of a sampled value in a serial manner. An ADC clock signal is used to drive the SAR ADC operation. The frequency of the ADC clock signal is a function of the sampling frequency and the number of cycles required per sample. Often, the ADC clock signal is derived from a phase lock loop (PLL) that is formed in the substrate of a system-on-chip (SOC). However, the frequencies used for optimal conversions for various applications are often difficult to meet using the limited selection of frequencies that can be derived from a PLL that is (e.g., beforehand) designed into an SOC.